This invention relates to semiconductor memory devices and methods of manufacture, and more particularly to construction of one-transistor dynamic read/write memory cells.
Dynamic read/write memory cells made by the double-level polysilicon N-channel self-aligned process commonly used in the industry for 16K and 64K DRAMs are shown in U.S. Pat. No. 4,388,121, issued to G. R. Mohan Rao, assigned to Texas Instruments. A contactless metal gate cell is shown in U.S. Pat. No. 4,345,364, issued to David J. McElroy, also assigned to Texas Instruments; this contactless cell can be made in higher density, such as needed for 256K and 1-Mbit DRAM devices.
Although these double-level polysilicon cells and contactless cells have proved to be quite successful and many hundreds of millions of memory devices have been made using such prior methods, there is nevertheless a continuing necessity to reduce the cell size, and increase the ratio of the storage capacitance per unit of cell area in dynamic memory cells, especially for the next generation 4-Mbit DRAMs. One improvement to this end has been to form the storage capacitor in a groove or trench so that the surface area of the capacitor is increased without increasing the cell area on the face of the chip; examples of this concept are shown in U.S. Pat. No. 4,225,945, issued to Kuo, or pending application Ser. No. 627,371, filed Jul. 3, 1984 by Baglee, Doering, & Armstrong, both assigned to Texas Instruments.
It is the principal object of this invention to provide an improved dynamic read/write memory cell, particularly of smaller cell size. An additional object is to provide a dense array of dynamic memory cells, made by a more efficient method. A further object is to provide an improved way of making dynamic memory cells.